CMOS image sensors are beginning to replace conventional CCD sensors for applications requiring image pickup such as digital cameras, cellular phones, PDA (personal digital assistant), personal computers, and the like. Advantageously, CMOS image sensors are fabricated by applying present CMOS fabricating process for semiconductor devices such as photodiodes or the like, at low costs. Furthermore, CMOS image sensors can be operated by a single power supply so that the power consumption for that can be restrained lower than that of CCD sensors, and further, CMOS logic circuits and like logic processing devices are easily integrated in the sensor chip and therefore the CMOS image sensors can be miniaturized.
FIG. 1 depicts a CMOS image sensor pixel array 10. As shown, the array comprises a plurality of microlenses 12, each having a hemisphere shape, arranged on a smooth planarization layer 17, e.g., a spin on polymer, that is formed on top of a color filter array 15 enabling formation of the microlens array. The color filter array 15 includes individual red, green and blue filter elements 25 (primary color filters) or alternately, cyan, magenta and yellow filter elements (complementary color filter). Each microlens 22 of the microlens array 12 is aligned with a corresponding color filter element 25 and comprises an upper light receiving portion of a pixel 20. The pixel 20 includes a cell portion fabricated upon a semiconductor substrate 14 portion including a stack of comprising one or more interlevel dielectric layers 30a-30c incorporating metallization interconnect levels M1, M2 Aluminum (Al) wire layers 35a, 35b. Interlevel dielectric materials may comprise a polymer or SiO2, for example. As Al metallization interconnect layers 35a, 35b do not require passivation, no respective barrier layers are shown.
As further shown in FIG. 1, each pixel cell 20 having the Al metallizations 35a, 35b further includes a final Aluminum metal level 36 that enables wire bonding to the M1 and M2 metallizations between each pixel 20, and a final passivation layer 28 is formed above the wire bonding level 36. This final passivation layer 28 may comprise SiN, SiO2, or combinations of these. Although not shown in detail, each pixel 20 includes a photoelectric converting device including a light sensitive element such as a photodiode 18 that performs photoelectric conversion and a CMOS transistor (not shown) that performs charge amplification and switching. Each of the pixels 20 generates a signal charge corresponding to the intensity of light received by each pixel and is converted to a signal current by the photoelectric conversion (photodiode) element 18 formed on semiconductor substrate 14. A further barrier or capping layer, e.g., a nitride such as SiN layer 38, is formed above unsilicided diffusion regions formed at the Si substrate 14 surface.
A protective film, such as a low temperature oxide (LTO), may be formed on microlenses to protect the microlenses during subsequent processing steps including sawing (e.g., cutting dicing, etc.) individual chips from a wafer. By changing the top surface of the structure from the hydrophobic microlenses to hydrophilic oxide, dicing dust is reduced since the surface becomes easier to rinse. However, the protective LTO layer suffers from cracking and/or delamination (e.g., peeling away from the microlens) during dicing, which disadvantageously reduces package yield. For example, FIGS. 2A-2C depict various magnifications of cracks 105 in an LTO layer. Also, FIGS. 3A-3C depict various magnifications of peeling (e.g., delamination) 110 of an LTO layer.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.